View HT16C24_5725062.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.30 1 april 02, 2012 rev. 1.00 pb april 02, 2012 HT16C24/HT16C24g ram mapping 72 4/68 8/60 16 lcd driver controller features ? operating voltage:2.4v ~ 5.5v ? internal 32khz rc oscillator ? bias: 1/3, 1/4 or 1/5; duty:1/4, 1/8 or 1/16 ? internal lcd bias generation with voltage-follower buffers ? i 2 c-bus interface ? two selectable lcd frame frequencies: 80hz or 160hz ? up to 60 x 16 bits ram for display data storage ? display patterns: C 72 4 patterns: 72 segments and 4 commons C 68 8 patterns: 68 segments and 8 commons C 60 16 patterns: 60 segments and 16 commons ? versatile blinking modes ? r/w address auto increment ? internal 16-step voltage adjustment to adjust lcd operating voltage ? low power consumption ? provides v lcd pin to adjust lcd operating voltage ? manufactured in silicon gate cmos process ? package type: 64-pin lqfp, 80-pin lqfp, chip and cog. applications ? electronic meter ? water meter ? gas meter ? heat energy meter ? household appliance ? games ? telephone ? consumer electronics general description the HT16C24/HT16C24g device is a memory mapping and multi-function lcd controller driver. the display segments of the device may be 288 patterns (72 segments and 4 commons), 544 patterns (68 segments and 8 commons) or 960 patterns (60 segments and 16 commons). the software configuration feature of the HT16C24/HT16C24g device makes it suitable for multiple lcd applications including lcd modules and display subsystems. the HT16C24/HT16C24g device communicates with most microprocessors / microcontrollers via a two- line bidirectional i 2 c-bus.
HT16C24/HT16C24g rev. 1.30 2 april 02, 2012 block diagram lcd voltage selector column /segment driver output segment driver output display ram 60*16bits timing generator i2c controller com0 com3 seg12 vlcd vss sda scl internal rc oscillator power_on reset r op1 com4/seg0 com15/seg11 r op2 seg71 vdd lcd bias generator r r op0 r op3 internal voltage adjustment op4
HT16C24/HT16C24g rev. 1.30 3 april 02, 2012 pin assignment seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 com8/seg4 com9/seg5 com10/seg6 com11/seg7 com12/seg8 com13/seg9 com14/seg10 com15/seg11 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 47 46 45 44 43 42 41 HT16C24 80 lqfp-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3738 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 40 49 48 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 vlcd com12/seg8 com13/seg9 com14/seg10 com15/seg11 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 com8/seg4 com9/seg5 com10/seg6 com11/seg7 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg68 seg69 seg70 vlcd 1 2 3 4 5 6 7 8 9 10 11 12 13 20 21 2223 2425 26 2728 6061626364 29303132 5253545556575859 14 15 16 43 44 45 46 47 48 36 37 38 39 40 41 42 33 34 35 1718 19 495051 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 HT16C24 64 lqfp-a note: application at v dd v lcd or v lcd v dd
HT16C24/HT16C24g rev. 1.30 4 april 02, 2012 pad assignment for cob seg53 seg52 seg51 seg50 seg49 seg48 seg47 seg46 seg45 seg44 seg43 seg42 seg41 seg40 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 seg65 seg66 seg67 seg68 seg69 seg70 seg71 vlcd vcca2 vdd sda scl vss com0 com1 com2 com3 com4/seg0 com5/seg1 com6/seg2 com7/seg3 com8/seg4 com9/seg5 com10/seg6 com11/seg7 com12/seg8 com13/seg9 com14/seg10 com15/seg11 seg12 seg13 seg14 seg15 1 n.c. 2 4 5 6 8 9 10 11 12 13 14 15 16 54 55 56 53 52 51 50 49 48 47 3 7 17 19 18 20 21 22 23 24 25 26 27 28 29 30 31 46 45 44 43 42 36 37 38 39 40 41 32 33 34 35 71 70 69 68 67 62 61 60 59 58 57 66 65 64 63 72 73 74 76 75 777879 81 80 8283 (0, 0) chip size: 2044 2438m 2 1rwhv7kh,vxevwudwhvkrxogehfrqqhfwhgwr9 66 lqwkh3odrxwduwzrun 9/'sdgdqg9sdgpxvweherqghgwrjhwkhuiruwkhdssolfdwlrqdw 9 '' 9 /' ru9 /' 9 '' internal voltage adjustment (iva) set command vlcd (pad 83) seg71 (pad 82) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 input null internal voltage adjustment is null vlcd support internal bias voltage 1 0 input output vlcd support internal bias voltage 1 1 input output vlcd support internal bias voltage 9''sdgdqg 9sdgpxvweherqghgwrjhwkhuiruwkhdssolfdwlrqdw9 /' 9 '' internal voltage adjustment (iva) set command vlcd (pad 83) seg71 (pad 82) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 output null detect the internal bias voltage vdd support internal bias voltage 1 0 floating output vdd support internal bias voltage 1 1 floating output vdd support internal bias voltage
HT16C24/HT16C24g rev. 1.30 5 april 02, 2012 pad coordinates for cob unit: m no name x y no name x y 1 vcca2 -734.6 1114.95 43 seg32 917.7 -993.1 2 vdd -918.4 889.55 44 seg33 917.7 -908.1 3 sda -918.4 804.55 45 seg34 917.7 -823.1 4 scl -918.4 719.55 46 seg35 917.7 -738.1 5 vss -918.4 634.55 47 seg36 917.7 -653.1 6 com0 -918.4 549.55 48 seg37 917.7 -568.1 7 com1 -918.4 464.55 49 seg38 917.7 -483.1 8 com2 -918.4 379.55 50 seg39 917.7 -398.1 9 com3 -918.4 294.55 51 seg40 917.7 -313.1 10 com4/seg0 -918.4 199.65 52 seg41 917.7 -228.1 11 com5/seg1 -918.4 114.65 53 seg42 917.7 -143.1 12 com6/seg2 -918.4 29.65 54 seg43 917.7 -58.1 13 com7/seg3 -918.4 -55.35 55 seg44 917.7 26.9 14 com8/seg4 -918.4 -140.35 56 seg45 917.7 111.9 15 com9/seg5 -918.4 -225.35 57 seg46 917.7 196.9 16 n.c. -567.474 -161.846 58 seg47 917.7 281.9 17 com10/seg6 -918.4 -310.35 59 seg48 917.7 366.9 18 com11/seg7 -918.4 -395.35 60 seg49 917.7 451.9 19 com12/seg8 -918.4 -480.35 61 seg50 917.7 536.9 20 com13/seg9 -918.4 -565.35 62 seg51 917.7 621.9 21 com14/seg10 -918.4 -650.35 63 seg52 917.7 706.9 22 com15/seg11 -918.4 -735.35 64 seg53 917.7 791.9 23 seg12 -918.4 -823.1 65 seg54 880.4 1114.95 24 seg13 -918.4 -908.1 66 seg55 795.4 1114.95 25 seg14 -918.4 -993.1 67 seg56 710.4 1114.95 26 seg15 -918.4 -1078.1 68 seg57 625.4 1114.95 27 seg16 -595.35 -1115.4 69 seg58 540.4 1114.95 28 seg17 -510.35 -1115.4 70 seg59 455.4 1114.95 29 seg18 -425.35 -1115.4 71 seg60 370.4 1114.95 30 seg19 -340.35 -1115.4 72 seg61 285.4 1114.95 31 seg20 -255.35 -1115.4 73 seg62 200.4 1114.95 32 seg21 -170.35 -1115.4 74 seg63 115.4 1114.95 33 seg22 -85.35 -1115.4 75 seg64 30.4 1114.95 34 seg23 -0.35 -1115.4 76 seg65 -54.6 1114.95 35 seg24 84.65 -1115.4 77 seg66 -139.6 1114.95 36 seg25 169.65 -1115.4 78 seg67 -224.6 1114.95 37 seg26 254.65 -1115.4 79 seg68 -309.6 1114.95 38 seg27 339.65 -1115.4 80 seg69 -394.6 1114.95 39 seg28 424.65 -1115.4 81 seg70 -479.6 1114.95 40 seg29 509.65 -1115.4 82 seg71 -564.6 1114.95 41 seg30 594.65 -1115.4 83 vlcd -649.6 1114.95 42 seg31 917.7 -1078.1
HT16C24/HT16C24g rev. 1.30 6 april 02, 2012 pad assignment for cog (0, 0) 2 3 4 5 6 7 8 9 10 11 12 13 14 1 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 44 45 42 43 40 41 3837363534333231302928272625242322 2120 1918 1716 15 39 59 58 57 56 55 54 53 52 51 50 49 48 47 46 note: ? vlcd (pad 20) must be connected to vcca2 (pad 21) in the pcb layout for the application at v dd v lcd or v lcd v dd . internal voltage adjustment (iva) set command vlcd (pad 20) seg71 (pad 13) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 input null internal voltage adjustment is null vlcd support internal bias voltage 1 0 input output vlcd support internal bias voltage 1 1 input output vlcd support internal bias voltage ? vdd (pad 18) must be connected to vcca2 (pad 21) in the pcb layout for the application at v lcd v dd . internal voltage adjustment (iva) set command vlcd (pad 20) seg71 (pad 13) note de bit ve bit 0 0 input null vlcd support internal bias voltage. 0 1 output null detect the internal bias voltage vdd support internal bias voltage 1 0 floating output vdd support internal bias voltage 1 1 floating output vdd support internal bias voltage pad dimensions for cog item number size unit x y chip size p 3958 1080 m chip thickness p 508 m pad pitch 1.3~15, 46~58, 60~121 60 m 16~45 87 m bump size output pad 62~120 40 60 m 5~13, 48~55 60 40 m input pad 16~21 67 67 m dummy pad 1, 60,61,121 40 60 m 3,4, 14,15, 46,47,56,57,58 60 40 m 22~45 67 67 m bump height all pad 183 m
HT16C24/HT16C24g rev. 1.30 7 april 02, 2012 alignment mark dimensions for cog item number size unit align_a 2 40um 20um (-1906, 362.5) 10um 10um 10um 10um m align_b 59 20um 20um 20um 20um (1886, 362.5) 10um 10um 10um 10um m
HT16C24/HT16C24g rev. 1.30 8 april 02, 2012 pad coordinates for cog unit: m no name x y no name x y 1 dummy -1866.85 444.5 63 com9/seg5 1673.15 444.5 3 dummy -1884.5 269.566 64 com10/seg6 1613.15 444.5 4 dummy -1884.5 209.566 65 com11/seg7 1553.15 444.5 5 seg63 -1884.5 149.566 66 com12/seg8 1493.15 444.5 6 seg64 -1884.5 89.566 67 com13/seg9 1433.15 444.5 7 seg65 -1884.5 29.566 68 com14/seg10 1373.15 444.5 8 seg66 -1884.5 -30.434 69 com15/seg11 1313.15 444.5 9 seg67 -1884.5 -90.434 70 seg12 1253.15 444.5 10 seg68 -1884.5 -150.434 71 seg13 1193.15 444.5 11 seg69 -1884.5 -210.434 72 seg14 1133.15 444.5 12 seg70 -1884.5 -270.434 73 seg15 1073.15 444.5 13 seg71 -1884.5 -330.434 74 seg16 1013.15 444.5 14 dummy -1884.5 -390.434 75 seg17 953.15 444.5 15 dummy -1884.5 -450.434 76 seg18 893.15 444.5 16 sda -1381.81 -436.691 77 seg19 833.15 444.5 17 scl -1294.81 -436.691 78 seg20 773.15 444.5 18 vdd -1023.81 -436.691 79 seg21 713.15 444.5 19 vss -936.81 -436.691 80 seg22 653.15 444.5 20 vlcd -750.81 -436.691 81 seg23 593.15 444.5 21 vcca2 -663.81 -436.691 82 seg24 533.15 444.5 22 dummy -477.81 -436.691 83 seg25 473.15 444.5 23 dummy -390.81 -436.691 84 seg26 413.15 444.5 24 dummy -303.81 -436.691 85 seg27 353.15 444.5 25 dummy -216.81 -436.691 86 seg28 293.15 444.5 26 dummy -129.81 -436.691 87 seg29 233.15 444.5 27 dummy -42.81 -436.691 88 seg30 173.15 444.5 28 dummy 44.19 -436.691 89 seg31 113.15 444.5 29 dummy 131.19 -436.691 90 seg32 53.15 444.5 30 dummy 218.19 -436.691 91 seg33 -6.85 444.5 31 dummy 305.19 -436.691 92 seg34 -66.85 444.5 32 dummy 392.19 -436.691 93 seg35 -126.85 444.5 33 dummy 479.19 -436.691 94 seg36 -186.85 444.5 34 dummy 566.19 -436.691 95 seg37 -246.85 444.5 35 dummy 653.19 -436.691 96 seg38 -306.85 444.5 36 dummy 740.19 -436.691 97 seg39 -366.85 444.5 37 dummy 827.19 -436.691 98 seg40 -426.85 444.5 38 dummy 914.19 -436.691 99 seg41 -486.85 444.5 39 dummy 1001.19 -436.691 100 seg42 -546.85 444.5 40 dummy 1088.19 -436.691 101 seg43 -606.85 444.5 41 dummy 1175.19 -436.691 102 seg44 -666.85 444.5 42 dummy 1262.19 -436.691 103 seg45 -726.85 444.5 43 dummy 1349.19 -436.691 104 seg46 -786.85 444.5 44 dummy 1436.19 -436.691 105 seg47 -846.85 444.5 45 dummy 1523.19 -436.691 106 seg48 -906.85 444.5 46 dummy 1884.5 -450.434 107 seg49 -966.85 444.5 47 dummy 1884.5 -390.434 108 seg50 -1026.85 444.5 48 com0 1884.5 -330.434 109 seg51 -1086.85 444.5
HT16C24/HT16C24g rev. 1.30 9 april 02, 2012 no name x y no name x y 49 com1 1884.5 -270.434 110 seg52 -1146.85 444.5 50 com2 1884.5 -210.434 111 seg53 -1206.85 444.5 51 com3 1884.5 -150.434 112 seg54 -1266.85 444.5 52 com4/seg0 1884.5 -90.434 113 seg55 -1326.85 444.5 53 com5/seg1 1884.5 -30.434 114 seg56 -1386.85 444.5 54 com6/seg2 1884.5 29.566 115 seg57 -1446.85 444.5 55 com7/seg3 1884.5 89.566 116 seg58 -1506.85 444.5 56 dummy 1884.5 149.566 117 seg59 -1566.85 444.5 57 dummy 1884.5 209.566 118 seg60 -1626.85 444.5 58 dummy 1884.5 269.566 119 seg61 -1686.85 444.5 60 dummy 1853.15 444.5 120 seg62 -1746.85 444.5 61 dummy 1793.15 444.5 121 dummy -1806.85 444.5 62 com8/seg4 1733.15 444.5 alignment mark coordinates for cog no name x y no name x y 2 align_a -1906 362.5 59 align_b 1886 362.5 pin/pad description pin name type description sda i/o serial data input/output for i 2 c interface scl i serial clock input for i 2 c interface vdd positive power supply. vss negative power supply, ground. vcca2 power supply for lcd bias generator vlcd one external resistor is connected between the vlcd pin and the vdd pin to determine the bias voltage for the package with a vlcd pin. internal voltage adjustment function is disabled. internal voltage adjustment function can be used to adjust the v lcd voltage. if the vlcd pin is used as a voltage output detection pin, an external power supply should not be applied to the vlcd pin. an external mcu can detect the voltage of the vlcd pin and program the internal voltage adjustment for the packages with a vlcd pin. com0~com3 o lcd common outputs. com4/seg0 ~com15/seg11 o lcd common/segment multiplexed driver outputs seg12~seg71 o lcd segment outputs.
HT16C24/HT16C24g rev. 1.30 10 april 02, 2012 approximate internal connections vdd vss scl, sda (for schmit trigger type) vselect-on vselect-off com0~com15; seg0~seg71 absolute maximum ratings supply voltage ....................................................................................................................... v ss -0.3v to v ss +6.5v input voltage ......................................................................................................................... v ss -0.3v to v dd +0.3v storage temperature ........................................................................................................................ -55c to 150c operating temperature ...................................................................................................................... -40c to 85c note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may af fect device reliability.
HT16C24/HT16C24g rev. 1.30 11 april 02, 2012 d.c. characteristics v ss = 0v; v dd =2.4 to 5.5v; ta = -40 to +85c symbol parameter test condition min. typ. max. unit v dd condition v dd operating voltage 2.4 5.5 v v lcd operating voltage 2.4 5.5 v i dd operating current 3v no load, v lcd =v dd, 1/3bias, f lcd =80hz, lcd display on, internal system oscillator on, da0~da3 are set to "0000" 30 45 a 5v 40 60 a i dd1 operating current 3v no load, v lcd =v dd, 1/3bias f lcd =80hz, lcd display off, internal system oscillator on, da0~da3 are set to 0000 2 5 a 5v 4 10 a i stb standby current 3v no load, v lcd =v dd , lcd display off, internal system oscillator off, 1 a 5v 2 a v ih input high voltage sda ,scl 0.7v dd v dd v v il input low voltage sda, scl 0 0.3v dd v i il input leakage current v in = v ss or v dd -1 1 a i ol low level output current 3v v ol =0.4v for sda 3 ma 5v 6 ma i ol1 lcd com sink current 3v v lcd =3v, v ol =0.3v 250 400 a 5v v lcd =5v, v ol =0.5v 500 800 a i oh1 lcd com source current 3v v lcd =3v, v oh =2.7v -140 -230 a 5v v lcd =5v, v oh =4.5v -300 -500 a i ol2 lcd seg sink current 3v v lcd =3v, v ol =0.3v 250 400 a 5v v lcd =5v, v ol =0.5v 500 800 a i oh2 lcd seg source current 3v v lcd =3v, v oh =2.7v -140 -230 a 5v v lcd =5v, v oh =4.5v -300 -500 a
HT16C24/HT16C24g rev. 1.30 12 april 02, 2012 a.c. characteristics v ss = 0v; v dd = 2.4 to 5.5v; ta= -40 to +85c symbol parameter test condition min. typ. max. unit v dd condition f lcd1 lcd frame frequency 4v 1/4 duty, ta =25 c 72 80 88 hz f lcd2 lcd frame frequency 4v 1/4 duty, ta =25 c 144 160 176 hz f lcd3 lcd frame frequency 4v 1/4 duty, ta=- 40 to +85c 52 80 124 hz f lcd4 lcd frame frequency 4v 1/4 duty, ta=- 40 to +85c 104 160 248 hz t off v dd off times v dd drop down to 0v 20 ms t sr v dd slew rate 0.05 v/ms note: ? if the conditions of power on reset timing are not satisfed during the power on/off sequence, the internal power on reset (por) circuit will not operate normally. ? if the v dd voltage drops below the minimum voltage of operating voltage spec. during operating, the power on reset timing conditions must also be satisfed. that is, the vdd voltage must drop to 0v and remain at 0v for 20ms (min.) before rising to the normal operating voltage. a.c. characteristics C i 2 c interface symbol parameter condition v dd =2.4v to 5.5v v dd =3.0v to 5.5v unit min. max. min. max. f scl clock frequency 100 400 khz t buf bus free time time in which the bus must be free before a new transmission can start 4.7 1.3 s t hd: sta start condition hold time after this period, the frst clock pulse is generated 4 0.6 s t low scl low time 4.7 1.3 s t high scl high time 4 0.6 s t su: sta start condition setup time only relevant for repeated start condition. 4.7 0.6 s t hd: dat data hold time 0 0 ns t su: dat data setup time 250 100 ns t r sda and scl rise time note 1 0.3 s t f sda and scl fall time note 0.3 0.3 s t su: sto stop condition set-up time 4 0.6 s t aa output valid from clock 3.5 0.9 s t sp input filter time constant (sda and scl pins) noise suppression time 100 50 ns note: these parameters are periodically sampled but not 100% tested.
HT16C24/HT16C24g rev. 1.30 13 april 02, 2012 timing diagrams i 2 c timing sda scl t f t hd:sta t low t r t hd:dat t su:dat t high t su:sta t hd:sta s sr t sp t su:sto p t buf s t aa sda out power on reset timing
HT16C24/HT16C24g rev. 1.30 14 april 02, 2012 output com3 com2 com1 com0 output com3 com2 com1 com0 address seg1 seg0 00h seg3 seg2 01h seg5 seg4 02h seg7 seg6 03h seg9 seg8 04h seg11 seg10 05h seg71 seg70 23h d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 72 4 display mode functional description power-on reset when the power is applied, the device is initialized by an internal power-on reset circuit. the status of the internal circuits after initialization is as follows: ? all common/segment outputs are set to v dd when v lcd v dd . ? all common/segment outputs are set to v lcd when v dd v lcd . ? the drive mode 1/4 duty output and 1/3 bias is selected. ? the system oscillator and the lcd bias generator are off state. ? lcd display is off state. ? internal voltage adjustment function is enabled. ? the segment/vlcd shared pin is set as the segment pin. ? detection switch for the vlcd pin is disabled. ? frame frequency is set to 80hz. ? blinking function is switched off data transfers on the i 2 c-bus should be avoided for 1ms following power-on to allow completion of the reset action. display memory C ram structure the display ram is static 60 16 bits ram which stores the lcd data. logic 1 in the ram bit-map indicates the on state of the corresponding lcd segment; similarly, logic 0 indicates the off state. the contents of the ram data are directly mapped to the lcd data. the frst ram column corresponds to the segments operated with respect to com0. in multiplexed lcd applications the segment data from 2nd to 16th column of the display ram are time- multiplexed from com1 to com15 respectively. the following is a mapping from the ram data to the lcd pattern:
HT16C24/HT16C24g rev. 1.30 15 april 02, 2012 output com7/ seg3 com6/ seg2 com5/ seg1 com4/ seg0 com3 com2 com1 com0 address seg4 00h seg5 01h seg6 02h seg7 03h seg8 04h seg9 05h seg71 43h d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 68 8 display mode output com15/seg11 com14/seg10 com13/seg9 com12/seg8 com11/seg7 com10/seg6 com9/seg5 com8/seg4 addr. com7/seg3 com6/seg2 com5/seg1 com4/seg0 com3 com2 com1 com0 addr. seg12 01h 00h seg13 03h 02h seg14 05h 04h seg15 07h 06h seg16 09h 08h seg17 0bh 0ah seg71 77h 76h d7 d6 d5 d4 d3 d2 d1 d0 data d7 d6 d5 d4 d3 d2 d1 d0 data ram mapping of 60 16 display mode d7 d6 d5 d4 d3 d2 d1 d0 msb lsb display data transfer format for i 2 c bus system oscillator the timing for the internal logic and the lcd drive signals are generated by an internal oscillator. the system clock frequency (f sys ) determines the lcd frame frequency. during initial system power on the system oscillator will be in the stop state.
HT16C24/HT16C24g rev. 1.30 16 april 02, 2012 seg n+2 seg n+2 seg n seg n com0 com0 com1 com1 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd com2 com2 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 seg n+3 seg n+3 com3 com3 seg n+1 seg n+1 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 v lcd v lcd v ss v ss v lcd - vop/3 v lcd - vop/3 v lcd - 2vop/3 v lcd - 2vop/3 waveforms for 1/4 duty drive mode with 1/3 bias (v op =v lcd -v ss ) note: t lcd =1/f lcd lcd bias generator the full-scale lcd voltage (vop) is obtained from (v lcd C v ss ). the lcd voltage may be temperature compensated externally through the voltage supply to the vlcd pin. fractional lcd biasing voltages, known as 1/3, 1/4 or 1/5 bias voltage, are obtained from an internal voltage divider of fve serial resistors connected between v lcd and v ss . the specifc resistor can be switched out of circuits to provide a 1/3, 1/4 or 1/5 bias voltage level confguration. lcd drive mode w aveforms ? when the lcd drive mode is selected as 1/4 duty and 1/3 bias, the waveform and lcd display is shown as follows:
HT16C24/HT16C24g rev. 1.30 17 april 02, 2012 ? when the lcd drive mode is selected as 1/8 duty and 1/4 bias, the waveform and lcd display is shown as follows: com0 com0 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com1 com1 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com2 com2 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com3 com3 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com4 com4 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com5 com5 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com6 com6 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 com7 com7 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n seg n v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+1 seg n+1 v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+2 seg n+2 v lcd v lcd v ss v ss v lcd - vop/4 v lcd - vop/4 v lcd - 2vop/4 v lcd - 2vop/4 v lcd - 3vop/4 v lcd - 3vop/4 seg n+3 seg n+3 v lcd v lcd waveforms for 1/8 duty drive mode with 1/4 bias (v op =v lcd -v ss ) note: t lcd =1/f lcd
HT16C24/HT16C24g rev. 1.30 18 april 02, 2012 ? when the lcd drive mode is selected as 1/16 duty and 1/5 bias, the waveform and lcd display is shown as follows: com0 com0 state1 (on) state1 (on) state2 (off) state2 (off) lcd segment lcd segment t lcd vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 com1 com1 seg n seg n vlcd- 4vop/5 vlcd- 4vop/5 vss vss vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com2 com2 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 com3 com3 vlcd- 4vop/5 vlcd- 4vop/5 vss vss vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com4 com4 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 com5 com5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com6 com6 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 com7 com7 vlcd- 4vop/5 vlcd- 4vop/5 vss vss vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com8 com8 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com9 com9 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com10 com10 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com11 com11 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com12 com12 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com13 com13 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com14 com14 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss com15 com15 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss seg n+1 seg n+1 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss seg n+2 seg n+2 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss seg n+3 seg n+3 vlcd vlcd vlcd- vop/5 vlcd- vop/5 vlcd- 2vop/5 vlcd- 2vop/5 vlcd- 3vop/5 vlcd- 3vop/5 vlcd- 4vop/5 vlcd- 4vop/5 vss vss waveforms for 1/16 duty drive mode with 1/5 bias (v op =v lcd -v ss ) note: t lcd =1/f lcd
HT16C24/HT16C24g rev. 1.30 19 april 02, 2012 blinking mode operating mode ratio blinking frequency (hz) 0 0 blink off 1 fsys / 16384hz 2 2 fsys / 32768hz 1 3 fsys / 65536hz 0.5 segment driver outputs the lcd drive section includes up to 72 segment outputs which should be connected directly to the lcd panel. the segment output signals are generated in accordance with the multiplexed column signals and with the data resident in the display latch. the unused segment outputs should be left open-circuit. column driver outputs the lcd drive section includes up to 16 column outputs which should be connected directly to the lcd panel. the column output signals are generated in accordance with the selected lcd drive mode. the unused column outputs should be left open-circuit. address pointer the addressing mechanism for the display ram is implemented using the address pointer. this allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display ram. the sequence commences with the initialization of the address pointer by the address pointer command. blinker function the device contains versatile blinking capabilities. the whole display can be blinked at frequencies selected by the blink command. the blinking frequency is a subdivided ratio of the system frequency. the ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table. frame frequency the HT16C24/HT16C24g device provides two frame frequencies selected with mode set command known as 80hz and 160hz respectively. internal v lcd voltage adjustment ? the internal v lcd adjustment contains four resistors in series and a 4-bit programmable analog switch which can provide sixteen voltage adjustment options using the v lcd voltage adjustment command. ? the internal v lcd adjustment structure is shown in the diagram: r internal voltage adjustment lcd bias generator v lcd pad r r r ve bit de bit v cca2 pad v dd pad r
HT16C24/HT16C24g rev. 1.30 20 april 02, 2012 ? the relationship between the programmable 4-bit analog switch and the vlcd output voltage is shown in the table: 1. when vcca2 pad is connected to vdd pad bias da3~da0 1/3 1/4 1/5 note 00h 1.000 v dd 1.000v dd 1.000v dd default value 01h 0.944 v dd 0.957v dd 0.966v dd 02h 0.894 v dd 0.918v dd 0.934v dd 03h 0.849 v dd 0.882v dd 0.904v dd 04h 0.808 v dd 0.849v dd 0.875v dd 05h 0.771 v dd 0.818v dd 0.849v dd 06h 0.738 v dd 0.789v dd 0.824v dd 07h 0.707 v dd 0.763v dd 0.801v dd 08h 0.678 v dd 0.738v dd 0.779v dd 09h 0.652 v dd 0.714v dd 0.758v dd 0ah 0.628 v dd 0.692v dd 0.738v dd 0bh 0.605 v dd 0.672v dd 0.719v dd 0ch 0.584 v dd 0.652v dd 0.701v dd 0dh 0.565 v dd 0.634v dd 0.684v dd 0eh 0.547 v dd 0.616v dd 0.668v dd 0fh 0.529 v dd 0.600 v dd 0.652v dd 2. when vcca2 pad is connected to vlcd pad bias da3~da0 1/3 1/4 1/5 note 00h 1.000v lcd 1.000v lcd 1.000v lcd default value 01h 0.944v lcd 0.957v lcd 0.966v lcd 02h 0.894v lcd 0.918v lcd 0.934v lcd 03h 0.849v lcd 0.882v lcd 0.904v lcd 04h 0.808v lcd 0.849v lcd 0.875v lcd 05h 0.771v lcd 0.818v lcd 0.849v lcd 06h 0.738v lcd 0.789v lcd 0.824v lcd 07h 0.707v lcd 0.763v lcd 0.801v lcd 08h 0.678v lcd 0.738v lcd 0.779v lcd 09h 0.652v lcd 0.714v lcd 0.758v lcd 0ah 0.628v lcd 0.692v lcd 0.738v lcd 0bh 0.605v lcd 0.672v lcd 0.719v lcd 0ch 0.584v lcd 0.652v lcd 0.701v lcd 0dh 0.565v lcd 0.634v lcd 0.684v lcd 0eh 0.547v lcd 0.616v lcd 0.668v lcd 0fh 0.529v lcd 0.600v lcd 0.652v lcd
HT16C24/HT16C24g rev. 1.30 21 april 02, 2012 i 2 c serial interface the device supports i 2 c serial interface. the i 2 c bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line, sda, and a serial clock line, scl. both lines are connected to the positive supply via pull-up resistors with a typical value of 4.7k. when the bus is free, both lines are high. devices connected to the bus must have open-drain or open-collector outputs to implement a wired- or function. data transfer is initiated only when the bus is not busy . data validity the data on the sda line must be stable during the high period of the serial clock. the high or low state of the data line can only change when the clock signal on the scl line is low as shown in the diagram. sda scl data line stable, data valid chang of data allowed start and stop conditions ? a high to low transition on the sda line while scl is high defnes a start condition. ? a low to high transition on the sda line while scl is high defnes a stop condition. ? start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. ? the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in some respects, the start(s) and repeated start (sr) conditions are functionally identical. p s sda scl sda scl start condition stop condition byte format every byte put on the sda line must be 8-bit long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most signifcant bit, msb, frst. s or sr p or sr sda scl 1 2 7 8 9 ack 1 2 3-8 9 ack p sr
HT16C24/HT16C24g rev. 1.30 22 april 02, 2012 acknowledge ? each bytes of eight bits is followed by one acknowledge bit. the acknowledge bit is a low level placed on the bus by the receiver. the master generates an extra acknowledge related clock pulse. ? a slave receiver which is addressed must generate an acknowledge bit, ack, after the reception of each byte. ? the device that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. ? a master receiver must signal an end of data to the slave by generating a not-acknowledge, nack, bit on the last byte that has been clocked out of the slave. in this case, the master receiver must leave the data line high during the 9 th pulse to not acknowledge. the master will generate a stop or repeated start condition. s 1 2 7 8 9 clock pulse for acknowledgement data output by transmitter data outptu by receiver scl from master acknowledge not acknowledge start condition s lave addressing ? the slave address byte is the frst byte received following the st ar t condition form the master device. the frst seven bits of the frst byte make up the slave address. the eighth bit defnes a read or write operation to be performed. when the r/ w bit is 1, then a read operation is selected. a 0 selects a write operation. ? the HT16C24/HT16C24g address bits are 0111101. when an address byte is sent, the device compares the frst seven bits after the start condition. if they match, the device outputs an acknowledge signal on the sda line. slave address 0 1 1 1 1 0 1 r/w msb lsb
HT16C24/HT16C24g rev. 1.30 23 april 02, 2012 write operation byte writes operation ? command byte a command byte write operation requires a start condition, a slave address with an r/ w bit, a command byte, a command setting byte and a stop condition for a command byte write operation. slave address ack write command byte ack s 0 1 1 1 1 0 1 0 1 st bit0bit1bit2bit3bit4bit5bit6bit7 command setting ack p 2 nd bit0bit1bit2bit3bit4bit5bit6bit7 command byte write operation ? display ram single data byte a display ram data byte write operation requires a start condition, a slave address with an r/ w bit, a command byte, a valid register address byte, a data byte and a stop condition. slave address ack write command byte ack s 0 1 1 1 1 0 1 0 data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 register address byte ack 2 nd 1 st bit0bit1bit2bit3bit4bit5bit6bit7 bit0bit1bit2bit3bit4bit5bit6bit7 display ram single data byte write operation display ram page write operation after a start condition the slave address with the r/ w bit is placed on the bus followed with a command byte and the specifed display ram register address of which the contents are written to the internal address pointer. the data to be written to the memory will be transmitted next and then the internal address pointer will be incremented by 1 to indicate the next memory address location after the reception of an acknowledge clock pulse. after the internal address point reaches the maximum memory address, which is 23h for 1/4 duty drive mode, 43h for 1/8 duty drive mode or 77h for 1/16 duty drive mode, the address pointer will be reset to 00h. slave address ack write ack s 0 1 1 1 1 0 1 0 ack 2 nd ack data byte p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack data byte d7 d6 d5 d4 d3 d2 d1 d0 1 st data ack register address byte command byte 1 st bit0bit1bit2bit3bit4bit5bit6bit7 bit0bit1bit2bit3bit4bit5bit6bit7 n bytes display ram data write operation
HT16C24/HT16C24g rev. 1.30 24 april 02, 2012 display ram read operation ? in this mode, the master reads theHT16C24/HT16C24g data after setting the slave address. following the r/w bit (=0) is an acknowledge bit, a command byte and the register address byte which is written to the internal address pointer. after the start address of the read operation has been confgured, another start condition and the slave address transferred on the bus followed by the r/ w bit (=1). then the msb of the data which was addressed is transmitted frst on the i 2 c bus. the address pointer is only incremented by 1 after the reception of an acknowledge clock. that means that if the device is confgured to transmit the data at the address of a n+1 , the master will read and acknowledge the transferred new data byte and the address pointer is incremented to a n+2 . after the internal address pointer reaches the maximum memory address, which is 23h for 1/4 duty drive mode, 43h for 1/8 duty drive mode or 77h for 1/16 duty drive mode, the address pointer will be reset to 00h. ? this cycle of reading consecutive addresses will continue until the master sends a st op condition. ack write ack p slave address s 0 1 1 1 1 0 1 0 data byte nack d7 d6 d5 d4 d3 d2 d1 d0 1 st data data byte ack p d7 d6 d5 d4 d3 d2 d1 d0 n th data data byte d7 d6 d5 d4 d3 d2 d1 d0 2 nd data ack ack ack device address read s 0 1 1 1 1 0 1 1 ack register address byte command byte 1 st 2 nd bit0bit1bit2bit3bit4bit5bit6bit7 bit0bit1bit2bit3bit4bit5bit6bit7
HT16C24/HT16C24g rev. 1.30 25 april 02, 2012 command summary display data input command this command sends data from mcu to memory map of the HT16C24/HT16C24g device. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def display data input/output command 1 st 1 0 0 0 0 0 0 0 w address pointer 2 nd x a6 a5 a4 a3 a2 a1 a0 display data start address of memory map w 00h note: power on status: the address is set to 00h if the programmed command is not defned, the function will not be af fected. for 1/4 duty drive mode after reaching the memory location 23h, the pointer will reset to 00h. for 1/8 duty drive mode after reaching the memory location 43h, the pointer will reset to 00h. for 1/16 duty drive mode after reaching the memory location 77h, the pointer will reset to 00h. drive mode command function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def driver mode setting command 1 st 1 0 0 0 0 0 1 0 w duty and bias setting 2 nd x x x x duty1 bias1 duty0 bias0 no matter what duty bit is set, 1/8 duty drive mode is only available for 48 lqfp. w 00h note: duty1 duty0 duty 0 0 1/4 duty 0 1 1/8 duty 1 x 1/16 duty bias1 bias0 bias 0 0 1/3 bias 0 1 1/4 bias 1 x 1/5 bias power on status: the drive mode 1/4 duty output and 1/3 bias is selected. if the programmed command is not defned, the function will not be af fected.
HT16C24/HT16C24g rev. 1.30 26 april 02, 2012 system mode command this command controls the internal system oscillator on/off and display on/off. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def system mode setting command 1 st 1 0 0 0 0 1 0 0 w system oscillator and display on/off setting 2 nd x x x x x x s e w 00h note: bit dutyinternal system oscillator lcd display s e 0 x off off 1 0 on off 1 1 on on power on status: display off and disable the internal system oscillator. if the programmed command is not defned, the function will not be af fected. frame frequency command this command selects the frame frequency. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def frame frequency command 1 st 1 0 0 0 0 1 1 0 w frame frequency setting 2 nd x x x x x x x f w 00h note: bit frame frequency f 0 80hz 1 160hz power on status: frame frequency is set to 80hz. if the programmed command is not defned, the function will not be af fected.
HT16C24/HT16C24g rev. 1.30 27 april 02, 2012 blinking frequency command this command defnes the blinking frequency of the display modes. function byte (msb) bit7 bit6 bit5 bit4 bit3 bit2 bit1 (lsb) bit0 note r/w def blinking frequency command 1 st 1 0 0 0 1 0 0 0 w blinking frequency setting 2 nd x x x x x x bk1 bk0 w 00h note: bit blinking frequency bk1 bk0 0 0 blinking off 0 1 2hz 1 0 1hz 1 1 0.5hz power on status: blinking function is switched off. if the programmed command is not defned, the function will not be af fected.
HT16C24/HT16C24g rev. 1.30 28 april 02, 2012 internal voltage adjustment (iva) setting command the internal voltage (v lcd ) adjustment can provide sixteen kinds of regulator voltage adjustment options by setting the lcd operating voltage adjustment command. function byte bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 note r/w def iva command 1 st 1 0 0 0 1 0 1 0 w iva control 2 nd x x de ve da3 da2 da1 da0 the segment/vlcd shared pin can be programmed via the de bit. the ve bit is used to enable or disable the internal voltage adjustment is supply voltage to bias voltage. the da3~da0 bits can be used to adjust the v lcd output voltage. w 30h note: bit segment 71/ vlcd shared pin select internal voltage adjustment note de ve 0 0 vlcd off the bias voltage is supplied by the external vlcd pin when vcca2 is connected to vlcd. the bias voltage is supplied by the external vlcd pin when vcca2 is connected to vdd. if the vlcd pin is connected to the vdd pin, the internal voltage follower (op4) must be disabled by setting the da3~da0 bits as 0000. 0 1 vlcd on when vcca2 is connected to vlcd, internal voltage adjustment can not be used to adjust internal bias voltage. (bias voltage is supplied by the external vlcd pin) when vcca2 is connected to vdd, internal voltage adjustment can not be used to adjust internal bias voltage when vlcd pin is supplies with external voltage.(recommend: can not be used) when vcca2 is connected to vdd, internal voltage adjustment can be used to adjust internal bias voltage when vlcd pin is foating and internal voltage adjustment is enable.(bias voltage is supplied by the internal voltage adjustment) 1 0 segment 71 off the bias voltage is supplied by the external vlcd pin when vcca2 is connected to vlcd. the bias voltage is supplied by the external vdd power when vcca2 is connected to vdd. th e internal voltage-follower (op4) is disabled automatically and da3~da0 dont care. 1 1 segment 71 on when vcca2 is connected to vlcd, internal voltage adjustment can be used to adjust internal bias voltage when vlcd pin is supplies with external voltage and internal voltage adjustment is enable. (bias voltage is supplied by the internal voltage adjustment) when vcca2 is connected to vdd, internal voltage adjustment can be used to adjust internal bias voltage when internal voltage adjustment is enable.(bias voltage is supplied by the internal voltage adjustment) power on status: enable the internal voltage adjustment and the segment/vlcd pin is set as the segment pin. when the da0~da3 bits are set to 0000, the internal voltage-follower (op4) is disabled. when the da0~da3 bits are set to other values except 0000, the internal voltage follower (op4) is enabled. if the programmed command is not defned, the function will not be af fected.
HT16C24/HT16C24g rev. 1.30 29 april 02, 2012 operation flow chart access procedures are illustrated below by means of the fowcharts. initialization power on segment / vlcd shared pin setting internal lcd frame frequency setting internal lcd bias and duty setting lcd blinking frequency setting next processing display data re ad/ write (address setting) start display on and internal system clock enabled display ram data write address setting next processing s egment/vlcd shared pin and internal voltage adjustment setting segment / vlcd share pin setting the bias voltage is supplied by programmable internal voltage adjustment one external resistor must be connected between to v lcd pin and v dd pin to determine the bias voltage internal voltage adjustment enable ? the external mcu can detect the voltage of vlcd pin yes no start s et as segment pin the bias voltage is supplied by internal vdd power next processing s et as vlcd pin internal voltage adjustment enable ? no yes
HT16C24/HT16C24g rev. 1.30 30 april 02, 2012 application circuits 1/4 duty HT16C24 lcd panel com0~com3 seg0~seg70 com0~com3 seg0~seg70 scl sda vdd vss host vdd vss vdd vss 0.1mf 4.7k w 4.7kw vlcd vlcd 0.1mf 1/8 duty HT16C24 lcd panel com0~com7 seg0~seg66 com0~com7 seg4~seg70 scl sda vdd vss host vdd vss vdd vss 0.1mf 4.7k w 4.7kw vlcd vlcd 0.1mf
HT16C24/HT16C24g rev. 1.30 31 april 02, 2012 1/16 duty HT16C24 lcd panel com0~com15 seg0~seg58 com0~com15 seg12~seg70 scl sda vdd vss host vdd vss vdd vss 0.1mf 4.7k w 4.7kw vlcd vlcd 0.1mf
HT16C24/HT16C24g rev. 1.30 32 april 02, 2012 package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 80-pin lqfp (10mm 10mm) outline dimensions lqfp outline dimensions 80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 0.476 b 0.390 0.398 c 0.469 0.476 d 0.390 0.398 e 0.016 f 0.006 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 11.90 12.10 b 9.90 10.10 c 11.90 12.10 d 9.90 10.10 e 0.40 f 0.16 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 package information 1 april 1, 2010 symbol dimensions in inch min. nom. max. a 0.469 D 0.476 b 0.390 D 0.398 c 0.469 D 0.476 d 0.390 D 0.398 e D 0.016 D f D 0.006 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 11.90 D 12.10 b 9.90 D 10.10 c 11.90 D 12.10 d 9.90 D 10.10 e D 0.40 D f D 0.16 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7
HT16C24/HT16C24g rev. 1.30 33 april 02, 2012 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.016 D f 0.005 D 0.009 g 0.053 D 0.057 h D D 0.063 i 0.002 D 0.006 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.13 D 0.23 g 1.35 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.20 0 D 7
HT16C24/HT16C24g rev. 1.30 34 april 02, 2012 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2012 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

▲Up To Search▲

Price & Availability of HT16C24

	To Download HT16C24 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .